1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a memory array with increased data throughput.
2. Description of the Related Art
Non-volatile read only memory (ROM) retains information even if power is cut off. Erasable ROM types comprise Mask ROM, EPROM, EEPROM, and Flash Memory, of which Mask ROM cannot modify stored data, and is suited to large fabrications. Additionally, Flash Memory, using electrons entering and exiting floating gate to store information, is non-volatile and accessible, and can also restore and access information even when power is not provided.
FIG. 1a is a cross section of a conventional flash memory unit during programming. When programming is performed, a high voltage is applied to a control gate electrode 105 and a drain region 101a, and then electrons penetrate through a gate oxide layer 102 to a floating gate electrode 103 from the drain region 101a in a silicon substrate 101.
FIG. 1b is a cross section of a conventional flash memory unit during erasure. When erasure is performed, a negative or zero voltage is applied to the control gate electrode 105, and a high voltage is applied to the drain region 101a in the silicon substrate 101. Electrons then penetrate through the gate oxide layer 102 back to the drain region 101a from the floating gate electrode 103.
As a result, one set of data can be programmed or erased each time by the conventional flash memory unit, that is, the maximum set count of data programmed or erased each time equals the number of memory units.
FIG. 1c is a cross section of a conventional programmed Mask ROM. The programming process is disclosed as follows. First, a silicon substrate 120 having a memory unit, such as a MOS transistor, thereon is provided. An oxide layer 122 is then formed over the silicon substrate 120. The memory unit comprises a gate electrode 123, such as a polysilicon layer, and source/drain regions 121a and 121b, such as n+ or p+ diffusion region, here, the source/drain regions 121a and 121b are n+ diffusion regions.
Next, a lithography process is performed using a code mask to form a patterned photoresist layer over a part of the gate electrode 123 and the source/drain regions 121a and 121b. Channel implantation with the silicon substrate 120 having memory units is then performed to complete the memory unit coding.
When the gate electrode 123 is uncovered by the patterned photoresist, the memory unit is defined as logic “1” due to implantation of the channel region 124, to the contrary, when the gate electrode 123 is covered by the patterned photoresist, the memory unit is defined as logic “0”, because the channel region 124 cannot be implanted.
Implantation Programming is completed by implanting ions into channel region to adjust the threshold voltage. This process is performed after forming the MOS transistor, and before forming contacts or inter layer dielectrics (ILD).
As integration density is increased, reduced time and memory unit size, and increased quantity and speed of data treatment are required for fabricating Mask ROMs.